1. Field of the Invention
The present invention relates clock circuitry to create a double clock frequency signal and/or delayed clock signal for a DDR-SDRAM memory controller to perform alignment of write access data and other signals.
2. The Prior Art
Double Data Rate (DDR) SDRAM devices can transfer data twice as fast as regular single data rate (SDR) SDRAM devices. This is because DDR-SDRAM devices can send and receive signals twice per clock cycle. This feature increases the complexity of receiving and sending data to or from the DDR-SDRAM device since the valid data windows are narrower than they are in SDR-SDRAM devices. FIGS. 1A and 1B illustrates the valid data windows for SDR-SDRAM devices and DDR-SDRAM devices.
In a typical application system such as a microcontroller circuit connected to DDR devices on a printed circuit board, DQS is a bidirectional control signal transmitted by the DDR-SDRAM devices during read operations and by the memory controller during write operations. The memory controller may be part of a microcontroller integrated circuit. As shown in FIGS. 2 and 3, for DDR device circuitry optimization, the DQS signal is provided edge-aligned with data for read operations and must be center-aligned with data for write operations. As shown in FIG. 2, it is common to use the falling edge of clock at twice the frequency of the system clock that drives DDR-SDRAM devices in order to write data to DDR-SDRAM devices without increasing the complexity of DDR-SDRAM controller and to guaranty that signal is center-aligned with data. FIG. 3 shows the use of a delayed DQS signal for reading data from DDR-SDRAM devices.
It would be advantageous to provide a system in which the signal required to provide the data alignment when write accesses are performed (2× clock or 90 degrees delayed) is independent of the clock driving other peripherals even if they are of the same frequency.